The present invention relates to a pixel conversion apparatus in an electronic equipment field taking a liquid crystal display as a representative. It relates to a pixel conversion apparatus, especially used when the number of pixels of the display area is different from the number of pixels of the input signal.
For displaying a picture on a display device such as a liquid crystal panel having different number of pixels from the pixels of an input signal, a pixel conversion apparatus is used. A pixel conversion apparatus in accordance with the prior art is explained below, referring to the drawing, to explain a function of scanning line conversion.
FIG. 1 is a block diagram of a pixel conversion apparatus in accordance with the prior art in the case of a reduction conversion. FIGS. 2(a)-2(h) are charts is a chart explaining a function of interpolating reduction conversion. In FIG. 1, the block 20 is a reference counter. The block 21 is a comparator. The block 22 is a register. The block 23 is an adder. The block 24 is an interpolation circuit. The block 25 is a memory. The block 26 is an address generator. FIGS. 2(a)-2(h) show shows a functional principle at reduction factor is 0.6. In FIGS. 2(a) and 2(h) short vertical lines of input signal express sample values of the original signal and the black dots express the values necessary to be newly made by interpolation. First, a reciprocal of the reduction factor EQU SH=(standard picture size)/(size to be reduced)
is inputted from, for example a microcomputer. In this example, EQU SH=1/0.6=1.67,
and it means that a new sample value is made at every 1.67 times of the original sampling period. In FIG. 2(c), the signal SH is applied to a .SIGMA.SH circuit 27 composed of register 22 and adder 23. .SIGMA.SH circuit 27 integrates the input signal at the output of comparator 21 at every time a coincidence pulse appears.
The integer part of the output signal of .SIGMA.SH circuit 27 which is an integral output is compared with the output of reference counter 20 (FIG. 2(b)) and comparator 21 outputs a coincidence pulse when the values are equal (FIG. 2(d)). The coincidence pulse indicates a position of a sample point to be interpolated, while the decimal part of the output signal of .SIGMA.SH circuit 27 is used as an interpolation coefficient at the moment. Thus, the sample value obtained as a result of interpolation is written (FIG. 2(e)) in a designated position on the main memory according to a writing address made from the coincidence pulse at the counter (FIG. 2(f)).
Thus, because a reduced image can be formed on the memory by interpolating new pixel data at a generation of coincidence pulse and writing in a main memory (FIG. 2(f)), if it is read at a standard speed (FIG. 2(g)) and is D/A converted, a reduced analog image signal is obtained (FIG. 2(h)). An example of a horizontal reduction is described but it is similar in a vertical reduction and in this case, a pulse synchronized with a horizontal sync signal takes a part of the clock signal.
To convert the number of sampling like this, it is necessary to calculate sampling points and interpolation coefficients for interpolation based on the reference clock (or horizontal sync pulse) and to form a data array by a memory.
Further, for example, considering a case to convert a VGA (video graphics array) standard into an XGA (extended video graphics array) standard and display it on a liquid crystal panel for XGA standard, the number of horizontal dots is 800 and the number of horizontal effective dots is 640 in the case of VGA standard. Because the number of horizontal effective dots is 1024 in the case of XGA, a signal of VGA standard can be displayed on a liquid crystal panel for XGA standard by multiplying the number of horizontal sampling by 1.6 (=1024/640).
A signal of 832 horizontal dots and 640 horizontal effective dots is included in a standard decided at VESA (Video Electronics Standards Association). When this signal is displayed for example, on a liquid crystal panel for XGA standard, if the number of horizontal effective dots is converted simply like multiplying by 1.6 (=1024/640), the number of horizontal dots becomes 1331.2 (=832.times.1.6), the number is an odd number with a decimal part and a normal display can not be obtained on this panel. Further, because the number of horizontal dots is larger than 1280 (standard of XGA), a part of image does not fill the specifications of a liquid crystal panel and it is sometimes impossible to display. Therefore, only the effective picture area of the converted signal is once written in a memory and only the effective picture area is read from the memory with a clock signal filling the specifications of the liquid crystal panel. In this case, it is general to adopt a method that reading clock signal is generated non-synchronized with the input signal, while the writing clock signal is synchronized with the input signal.
For a television signal such as NTSC (National Television Standard Committee), a composition to display on a panel having VGA of 640.times.480 pixels by doubling the number of scanning lines is generally used. In this case, to double the number of scanning lines, a composition to convert the number of scanning lines into double by writing the input signal into a FIFO (first in and first out) and reading a line twice at a double speed of the writing is generally used. The composition is simple and there is no need of a field memory and only an FIFO (line memory) is necessary but the vertical resolution deteriorates because it is not interlaced. To secure a good vertical resolution, a field memory such as movement adaptive type scanning line interpolation is necessary.
A plurality of clock signal generation circuits for writing and reading into and from a memory used for a pixel conversion of the prior art is explained below and a plurality of PLL (phase locked loop) circuits having the same composition are merely used for generating each clock signal.
FIG. 3 is a block diagram of a video display apparatus in accordance with the prior art. The block 1 is a sync separator. The block 2 is a first phase detector. The block 3 is a first LPF (low pass filter). The block 4 is a first VCO (voltage controlled oscillator). The block 5 is a first counter. The block 6 is a first PLL composed of first phase detector 2, first LPF 3, first VCO 4 and first counter 5. The block 7 is a pixel converter. The block 8 is a second phase detector. The block 9 is a second LPF. The block 10 is a second VCO. The block 11 is a second counter. The block 12 is a second PLL composed of second phase detector 8, second LPF 9, second VCO 10 and second counter 11. The block 13 is a timing signal generator.
A composite video signal inputted from an outside is supplied to pixel converter 7, an expansion or a reduction is processed by a clock signal from first PLL 6 and a clock signal from second PLL 12. (Clock signals having different frequencies are used between the input and the output.)
The composite video signal inputted from the outside is also supplied to sync separator 1 at the same time. At sync separator 1, only a sync signal is extracted from the composite video signal. A horizontal sync signal separated at sync separator 1 is supplied to first phase comparator 2. The PWM (pulse width modulation) output of first phase comparator 2 is supplied to first LPF 3. The response characteristic of first PLL 6 is almost decided at first LPF 3. Receiving an output of first LPF 3, first VCO 4 outputs a stable first clock signal. This first clock signal is used for driving a front stage of pixel converter 7. Further, the first clock signal is frequency divided at an arbitrary rate at first counter 5 and is returned to first phase detector 2. A phase difference between two input signals is detected at first phase comparator 2. The output of first counter 5 is also supplied to second phase comparator 8. The response characteristic of second PLL 12 is decided at second LPF 9.
In the case in which pixel interpolation is necessary at a pixel conversion apparatus in accordance with the prior art, what interpolation is made is explained below. A horizontal pixel conversion circuit of the prior art is explained below referring to the drawings. FIG. 4 is a block diagram of a horizontal pixel conversion circuit of the prior art. PLL circuit 42 is a circuit for faithfully reproducing a clock signal forming the input signal from the input signal and it is necessary to know previously and correctly the number of clocks per one horizontal period and the phase difference between the input signal and the clock a reproduced at PLL circuit 42 has to be adjusted. In recent years, signals outputted from computers have a lot of variety, for example the clock frequency has a wide range from about 20 MHz to over 100 MHZ. At any two computers, the numbers of clocks per one horizontal period including a blanking period are not always the same, even if the number of effective display pixels of the two computers are the same. With what clock frequency or with what number of clocks per one horizontal period, the operator of the computer or the software of the computer outputs a signal is quite arbitrary. Therefore, the oscillation frequency range of PLL circuit 42 must be wide and a lot of values must be previously stored for the number of clocks per one horizontal period.
The function of a gradation integral display circuit 43 is expressed by the following equation. EQU Qi=D(i).times.a+D(i+1).times.b+D(i+2).times.c+D(i+3).times.d
Where, Qi is the i-th data after pixel conversion. D(i+1), D(i+2) and D(i+3) are the D(i+1)-th, the D(i+2)-th and the D(i+3)-th data before conversion, respectively. For example, the values a, b, c and d of the input signal are decided by a ratio of number of pixels between before and after conversion and is obtained by calculating a contribution factor of the data before conversion against the data after conversion. An example of the gradation integral display at a conversion from five pixels to four pixels is shown in FIGS. 5(a) and 5(b). As shown in FIG. 5(a), the five pixels before conversion are divided into four equal parts and, as shown in FIG. 5(b), new brightness values for the four pixels are obtained by integrating each brightness value at each divided area. Information which originally one pixel had is reflected to one or two pixels after pixel conversion.